Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.4 (ISE) - M.81d Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx9
Project ID (random number) 7e64947bca0e405d972361607b7f3a9f.04689F3BEAEA42038E5FFDBAACC5B076.1 Target Package: tqg144
Registration ID 15690819_173552794_661 Target Speed: -2
Date Generated 2011-09-29T15:28:04 Tool Flow ISE
 
User Environment
OS Name Microsoft OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-2620M CPU @ 2.70GHz CPU Speed 2693 MHz
OS Name Microsoft OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-2620M CPU @ 2.70GHz CPU Speed 2693 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=1
  • 26-bit comparator not equal=1
 Counters=1
  • 13-bit up counter=1
 Registers=53
  • Flip-Flops=53
 		MiscellaneousStatistics
  • AGG_BONDED_IO=25
  • AGG_IO=25
  • AGG_LOCED_IO=1
  • AGG_SLICE=175
  • NUM_BONDED_IOB=25
  • NUM_BSCAN=1
  • NUM_BSFULL=279
  • NUM_BSLUTONLY=100
  • NUM_BSREGONLY=122
  • NUM_BSUSED=501
  • NUM_BUFG=2
  • NUM_LOCED_IOB=1
  • NUM_LOGIC_O5ANDO6=39
  • NUM_LOGIC_O5ONLY=71
  • NUM_LOGIC_O6ONLY=110
  • NUM_LUT_RT_DRIVES_CARRY4=10
  • NUM_LUT_RT_DRIVES_FLOP=61
  • NUM_LUT_RT_EXO5=54
  • NUM_LUT_RT_EXO6=10
  • NUM_LUT_RT_O5=14
  • NUM_LUT_RT_O5ANDO6=7
  • NUM_LUT_RT_O6=70
  • NUM_RAMB16BWER=26
  • NUM_RPM=9
  • NUM_SLICEL=41
  • NUM_SLICEM=36
  • NUM_SLICEX=98
  • NUM_SLICE_CARRY4=46
  • NUM_SLICE_CONTROLSET=54
  • NUM_SLICE_CYINIT=523
  • NUM_SLICE_F7MUX=11
  • NUM_SLICE_F8MUX=2
  • NUM_SLICE_FF=486
  • NUM_SLICE_LATCH=1
  • NUM_SLICE_UNUSEDCTRL=4
  • NUM_SRL_O5ONLY=2
  • NUM_SRL_O6ONLY=86
  • NUM_UNUSABLE_FF_BELS=273
  • Xilinx Core chipscope_icon_v1_04_a, Xilinx CORE Generator 12.4=1
  • Xilinx Core chipscope_ila_v1_03_a, Xilinx CORE Generator 12.4=1
  • Xilinx Core dds_compiler_v4_0, Xilinx CORE Generator 12.4=1
 		NetStatistics
  • NumNets_Active=728
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=23
  • NumNodesOfType_Active_BOUNCEIN=123
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=14
  • NumNodesOfType_Active_CLKPIN=171
  • NumNodesOfType_Active_CLKPINFEED=19
  • NumNodesOfType_Active_CNTRLPIN=158
  • NumNodesOfType_Active_DOUBLE=1463
  • NumNodesOfType_Active_GENERIC=25
  • NumNodesOfType_Active_GLOBAL=92
  • NumNodesOfType_Active_INPUT=1008
  • NumNodesOfType_Active_IOBIN2OUT=24
  • NumNodesOfType_Active_IOBOUTPUT=24
  • NumNodesOfType_Active_LUTINPUT=885
  • NumNodesOfType_Active_OUTBOUND=724
  • NumNodesOfType_Active_OUTPUT=725
  • NumNodesOfType_Active_PADINPUT=24
  • NumNodesOfType_Active_PADOUTPUT=1
  • NumNodesOfType_Active_PINBOUNCE=675
  • NumNodesOfType_Active_PINFEED=2018
  • NumNodesOfType_Active_QUAD=1536
  • NumNodesOfType_Active_REGINPUT=244
  • NumNodesOfType_Active_SINGLE=1642
  • NumNodesOfType_Gnd_BOUNCEIN=97
  • NumNodesOfType_Gnd_DOUBLE=2
  • NumNodesOfType_Gnd_HGNDOUT=66
  • NumNodesOfType_Gnd_INPUT=178
  • NumNodesOfType_Gnd_LUTINPUT=31
  • NumNodesOfType_Gnd_OUTBOUND=3
  • NumNodesOfType_Gnd_OUTPUT=4
  • NumNodesOfType_Gnd_PINBOUNCE=123
  • NumNodesOfType_Gnd_PINFEED=181
  • NumNodesOfType_Gnd_REGINPUT=24
  • NumNodesOfType_Gnd_SINGLE=1
  • NumNodesOfType_Vcc_CNTRLPIN=8
  • NumNodesOfType_Vcc_HVCCOUT=172
  • NumNodesOfType_Vcc_INPUT=1854
  • NumNodesOfType_Vcc_KVCCOUT=141
  • NumNodesOfType_Vcc_LUTINPUT=393
  • NumNodesOfType_Vcc_PINBOUNCE=213
  • NumNodesOfType_Vcc_PINFEED=2047
  • NumNodesOfType_Vcc_REGINPUT=5
 SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=13
  • IOB-IOBS=12
  • SLICEL-SLICEM=28
  • SLICEX-SLICEL=20
  • SLICEX-SLICEM=13
 		SiteSummary
  • BSCAN=1
  • BSCAN_BSCAN=1
  • BUFG=2
  • BUFG_BUFG=2
  • CARRY4=46
  • FF_SR=87
  • HARD0=4
  • HARD1=10
  • IOB=25
  • IOB_IMUX=1
  • IOB_INBUF=1
  • IOB_OUTBUF=24
  • LUT5=179
  • LUT6=231
  • LUT_OR_MEM5=8
  • LUT_OR_MEM6=91
  • PAD=25
  • RAMB16BWER=26
  • RAMB16BWER_RAMB16BWER=26
  • REG_SR=400
  • SELMUX2_1=13
  • SLICEL=41
  • SLICEM=36
  • SLICEX=98
 
Configuration Data
BSCAN_BSCAN
  • JTAG_CHAIN=[1:1]
  • JTAG_TEST=[0:1]
 FF_SR
  • CK=[CK:87] [CK_INV:0]
  • SRINIT=[SRINIT0:62] [SRINIT1:25]
  • SYNC_ATTR=[ASYNC:69] [SYNC:18]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:24]
  • SLEW=[SLOW:24]
  • SUSPEND=[3STATE:24]
 LUT_OR_MEM5
  • CLK=[CLK:2] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:6] [RAM:2]
  • RAMMODE=[SRL16:2]
 LUT_OR_MEM6
  • CLK=[CLK:86] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:5] [RAM:86]
  • RAMMODE=[SRL16:51] [SRL32:35]
 RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:26]
  • CLKB=[CLKB_INV:0] [CLKB:26]
  • ENA=[ENA_INV:0] [ENA:26]
  • ENB=[ENB_INV:0] [ENB:26]
  • REGCEA=[REGCEA_INV:0] [REGCEA:26]
  • REGCEB=[REGCEB_INV:0] [REGCEB:26]
  • RSTA=[RSTA:26] [RSTA_INV:0]
  • RSTB=[RSTB:26] [RSTB_INV:0]
  • WEA0=[WEA0:26] [WEA0_INV:0]
  • WEA1=[WEA1:26] [WEA1_INV:0]
  • WEA2=[WEA2:26] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:26]
  • WEB0=[WEB0:26] [WEB0_INV:0]
  • WEB1=[WEB1:26] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:26]
  • WEB3=[WEB3:26] [WEB3_INV:0]
 RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:26]
  • CLKB=[CLKB_INV:0] [CLKB:26]
  • DATA_WIDTH_A=[1:25] [18:1]
  • DATA_WIDTH_B=[1:25] [18:1]
  • DOA_REG=[0:25] [1:1]
  • DOB_REG=[0:25] [1:1]
  • ENA=[ENA_INV:0] [ENA:26]
  • ENB=[ENB_INV:0] [ENB:26]
  • EN_RSTRAM_A=[FALSE:25] [TRUE:1]
  • EN_RSTRAM_B=[FALSE:25] [TRUE:1]
  • RAM_MODE=[TDP:26]
  • REGCEA=[REGCEA_INV:0] [REGCEA:26]
  • REGCEB=[REGCEB_INV:0] [REGCEB:26]
  • RSTA=[RSTA:26] [RSTA_INV:0]
  • RSTB=[RSTB:26] [RSTB_INV:0]
  • RSTTYPE=[SYNC:26]
  • RST_PRIORITY_A=[CE:26]
  • RST_PRIORITY_B=[CE:26]
  • WEA0=[WEA0:26] [WEA0_INV:0]
  • WEA1=[WEA1:26] [WEA1_INV:0]
  • WEA2=[WEA2:26] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:26]
  • WEB0=[WEB0:26] [WEB0_INV:0]
  • WEB1=[WEB1:26] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:26]
  • WEB3=[WEB3:26] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:26]
  • WRITE_MODE_B=[WRITE_FIRST:26]
 REG_SR
  • CK=[CK:399] [CK_INV:1]
  • LATCH_OR_FF=[FF:399] [LATCH:1]
  • SRINIT=[SRINIT0:340] [SRINIT1:60]
  • SYNC_ATTR=[ASYNC:247] [SYNC:153]
 SLICEL
  • CLK=[CLK:40] [CLK_INV:0]
 SLICEM
  • CLK=[CLK:36] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:94] [CLK_INV:1]
 
Pin Data
BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
 BSCAN_BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
 BUFG
  • I0=2
  • O=2
 BUFG_BUFG
  • I0=2
  • O=2
 CARRY4
  • CIN=32
  • CO0=4
  • CO3=32
  • CYINIT=14
  • DI0=40
  • DI1=34
  • DI2=34
  • DI3=32
  • O0=36
  • O1=34
  • O2=28
  • O3=28
  • S0=46
  • S1=40
  • S2=34
  • S3=34
 FF_SR
  • CE=5
  • CK=87
  • D=87
  • Q=87
  • SR=34
 HARD0
  • 0=4
 HARD1
  • 1=10
 IOB
  • I=1
  • O=24
  • PAD=25
 IOB_IMUX
  • I=1
  • OUT=1
 IOB_INBUF
  • OUT=1
  • PAD=1
 IOB_OUTBUF
  • IN=24
  • OUT=24
 LUT5
  • A1=1
  • A2=4
  • A3=12
  • A4=27
  • A5=71
  • O5=179
 LUT6
  • A1=25
  • A2=42
  • A3=74
  • A4=203
  • A5=123
  • A6=217
  • O6=231
 LUT_OR_MEM5
  • A1=3
  • A2=3
  • A3=4
  • A4=3
  • A5=6
  • CLK=2
  • DI1=2
  • O5=8
  • WE=2
 LUT_OR_MEM6
  • A1=86
  • A2=86
  • A3=86
  • A4=91
  • A5=87
  • A6=91
  • CLK=86
  • DI1=35
  • DI2=51
  • MC31=57
  • O6=91
  • WE=86
 PAD
  • PAD=25
 RAMB16BWER
  • ADDRA0=25
  • ADDRA1=25
  • ADDRA10=26
  • ADDRA11=26
  • ADDRA12=26
  • ADDRA13=26
  • ADDRA2=25
  • ADDRA3=25
  • ADDRA4=26
  • ADDRA5=26
  • ADDRA6=26
  • ADDRA7=26
  • ADDRA8=26
  • ADDRA9=26
  • ADDRB0=25
  • ADDRB1=25
  • ADDRB10=26
  • ADDRB11=26
  • ADDRB12=26
  • ADDRB13=26
  • ADDRB2=25
  • ADDRB3=25
  • ADDRB4=26
  • ADDRB5=26
  • ADDRB6=26
  • ADDRB7=26
  • ADDRB8=26
  • ADDRB9=26
  • CLKA=26
  • CLKB=26
  • DIA0=26
  • DIA1=26
  • DIA10=26
  • DIA11=26
  • DIA12=26
  • DIA13=26
  • DIA14=26
  • DIA15=26
  • DIA16=25
  • DIA17=25
  • DIA18=25
  • DIA19=25
  • DIA2=26
  • DIA20=25
  • DIA21=25
  • DIA22=25
  • DIA23=25
  • DIA24=25
  • DIA25=25
  • DIA26=25
  • DIA27=25
  • DIA28=25
  • DIA29=25
  • DIA3=26
  • DIA30=25
  • DIA31=25
  • DIA4=26
  • DIA5=26
  • DIA6=26
  • DIA7=26
  • DIA8=26
  • DIA9=26
  • DIB0=25
  • DIB1=25
  • DIB10=25
  • DIB11=25
  • DIB12=25
  • DIB13=25
  • DIB14=25
  • DIB15=25
  • DIB16=25
  • DIB17=25
  • DIB18=25
  • DIB19=25
  • DIB2=25
  • DIB20=25
  • DIB21=25
  • DIB22=25
  • DIB23=25
  • DIB24=25
  • DIB25=25
  • DIB26=25
  • DIB27=25
  • DIB28=25
  • DIB29=25
  • DIB3=25
  • DIB30=25
  • DIB31=25
  • DIB4=25
  • DIB5=25
  • DIB6=25
  • DIB7=25
  • DIB8=25
  • DIB9=25
  • DIPA0=26
  • DIPA1=26
  • DIPA2=25
  • DIPA3=25
  • DIPB0=25
  • DIPB1=25
  • DIPB2=25
  • DIPB3=25
  • DOA0=26
  • DOA1=1
  • DOA10=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOB0=1
  • DOB1=1
  • DOB10=1
  • DOB2=1
  • DOB3=1
  • DOB4=1
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • ENA=26
  • ENB=26
  • REGCEA=26
  • REGCEB=26
  • RSTA=26
  • RSTB=26
  • WEA0=26
  • WEA1=26
  • WEA2=26
  • WEA3=26
  • WEB0=26
  • WEB1=26
  • WEB2=26
  • WEB3=26
 RAMB16BWER_RAMB16BWER
  • ADDRA0=25
  • ADDRA1=25
  • ADDRA10=26
  • ADDRA11=26
  • ADDRA12=26
  • ADDRA13=26
  • ADDRA2=25
  • ADDRA3=25
  • ADDRA4=26
  • ADDRA5=26
  • ADDRA6=26
  • ADDRA7=26
  • ADDRA8=26
  • ADDRA9=26
  • ADDRB0=25
  • ADDRB1=25
  • ADDRB10=26
  • ADDRB11=26
  • ADDRB12=26
  • ADDRB13=26
  • ADDRB2=25
  • ADDRB3=25
  • ADDRB4=26
  • ADDRB5=26
  • ADDRB6=26
  • ADDRB7=26
  • ADDRB8=26
  • ADDRB9=26
  • CLKA=26
  • CLKB=26
  • DIA0=26
  • DIA1=26
  • DIA10=26
  • DIA11=26
  • DIA12=26
  • DIA13=26
  • DIA14=26
  • DIA15=26
  • DIA16=25
  • DIA17=25
  • DIA18=25
  • DIA19=25
  • DIA2=26
  • DIA20=25
  • DIA21=25
  • DIA22=25
  • DIA23=25
  • DIA24=25
  • DIA25=25
  • DIA26=25
  • DIA27=25
  • DIA28=25
  • DIA29=25
  • DIA3=26
  • DIA30=25
  • DIA31=25
  • DIA4=26
  • DIA5=26
  • DIA6=26
  • DIA7=26
  • DIA8=26
  • DIA9=26
  • DIB0=25
  • DIB1=25
  • DIB10=25
  • DIB11=25
  • DIB12=25
  • DIB13=25
  • DIB14=25
  • DIB15=25
  • DIB16=25
  • DIB17=25
  • DIB18=25
  • DIB19=25
  • DIB2=25
  • DIB20=25
  • DIB21=25
  • DIB22=25
  • DIB23=25
  • DIB24=25
  • DIB25=25
  • DIB26=25
  • DIB27=25
  • DIB28=25
  • DIB29=25
  • DIB3=25
  • DIB30=25
  • DIB31=25
  • DIB4=25
  • DIB5=25
  • DIB6=25
  • DIB7=25
  • DIB8=25
  • DIB9=25
  • DIPA0=26
  • DIPA1=26
  • DIPA2=25
  • DIPA3=25
  • DIPB0=25
  • DIPB1=25
  • DIPB2=25
  • DIPB3=25
  • DOA0=26
  • DOA1=1
  • DOA10=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOB0=1
  • DOB1=1
  • DOB10=1
  • DOB2=1
  • DOB3=1
  • DOB4=1
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • ENA=26
  • ENB=26
  • REGCEA=26
  • REGCEB=26
  • RSTA=26
  • RSTB=26
  • WEA0=26
  • WEA1=26
  • WEA2=26
  • WEA3=26
  • WEB0=26
  • WEB1=26
  • WEB2=26
  • WEB3=26
 REG_SR
  • CE=116
  • CK=400
  • D=400
  • Q=400
  • SR=212
 SELMUX2_1
  • 0=13
  • 1=13
  • OUT=13
  • S0=13
 SLICEL
  • A=2
  • A1=1
  • A2=1
  • A3=6
  • A4=36
  • A5=10
  • A6=33
  • AMUX=3
  • AQ=40
  • AX=9
  • B=2
  • B1=1
  • B2=2
  • B3=6
  • B4=34
  • B5=10
  • B6=30
  • BMUX=3
  • BQ=33
  • BX=7
  • C1=3
  • C2=4
  • C3=8
  • C4=32
  • C5=12
  • C6=31
  • CE=18
  • CIN=28
  • CLK=40
  • CMUX=6
  • COUT=26
  • CQ=28
  • CX=10
  • D1=4
  • D2=4
  • D3=7
  • D4=30
  • D5=11
  • D6=31
  • DMUX=2
  • DQ=28
  • DX=6
  • SR=24
 SLICEM
  • A=16
  • A1=34
  • A2=34
  • A3=34
  • A4=36
  • A5=35
  • A6=36
  • AI=22
  • AMUX=4
  • AQ=10
  • AX=13
  • B=1
  • B1=19
  • B2=19
  • B3=19
  • B4=20
  • B5=20
  • B6=20
  • BI=6
  • BMUX=4
  • BQ=9
  • BX=11
  • C=4
  • C1=20
  • C2=20
  • C3=21
  • C4=21
  • C5=21
  • C6=19
  • CE=36
  • CI=9
  • CIN=4
  • CLK=36
  • CMUX=3
  • COUT=6
  • CQ=7
  • CX=9
  • D=2
  • D1=16
  • D2=16
  • D3=16
  • D4=16
  • D5=17
  • D6=16
  • DI=14
  • DMUX=26
  • DQ=8
  • DX=10
  • SR=2
 SLICEX
  • A=22
  • A1=7
  • A2=14
  • A3=20
  • A4=30
  • A5=49
  • A6=33
  • AMUX=25
  • AQ=82
  • AX=70
  • B=18
  • B1=6
  • B2=8
  • B3=19
  • B4=26
  • B5=37
  • B6=26
  • BMUX=20
  • BQ=58
  • BX=47
  • C=9
  • C1=3
  • C2=7
  • C3=9
  • C4=15
  • C5=28
  • C6=16
  • CE=23
  • CLK=95
  • CMUX=20
  • CQ=47
  • CX=39
  • D=9
  • D1=1
  • D2=4
  • D3=7
  • D4=13
  • D5=22
  • D6=17
  • DMUX=15
  • DQ=50
  • DX=42
  • SR=63
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
_impact 20 16 0 0 0 0 0
arwz 11 11 0 0 0 0 0
bitgen 26 26 0 0 0 0 0
cse_server 12 12 0 0 0 0 0
edif2ngd 36 36 0 0 0 0 0
elfcheck 49 48 0 0 0 0 0
libgen 6 6 0 0 0 0 0
map 57 44 0 0 0 0 0
netgen 35 35 0 0 0 0 0
ngc2edif 6 6 0 0 0 0 0
ngcbuild 119 119 0 0 0 0 0
ngdbuild 66 66 0 0 0 0 0
obngc 5 5 0 0 0 0 0
par 44 44 0 0 0 0 0
platgen 7 7 0 0 0 0 0
psf2Edward 7 7 0 0 0 0 0
trce 42 42 0 0 0 0 0
xawinfo 9 9 0 0 0 0 0
xbash 2 1 0 0 0 0 0
xdsgen 6 6 0 0 0 0 0
xps 33 16 0 0 0 0 0
xst 234 231 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/cgn_c_cust_gui_overview.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2011-09-29T14:54:16
PROP_intWbtProjectID=04689F3BEAEA42038E5FFDBAACC5B076 PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx9
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=tqg144
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-2
PROP_PreferredLanguage=Verilog FILE_CDC=1
FILE_COREGEN=1 FILE_UCF=1
FILE_VERILOG=2
 
PlanAhead Usage
Project Data
SrcSetCount=1 ConstraintSetCount=1 DesignMode=RTL SynthesisStrategy=PlanAhead Defaults
ImplStrategy=ISE Defaults
Java Command Handlers
AddConstraint=1 AddCreateSrc=1 ConfigureBitgenRun=1 ConfigureImplRun=2
ConfigureSynthRun=2 CoreView=2 CreateHistogram=1 CreateProject=2
ImportTiming=1 ReportTiming=2 RunDesignAhead=2 RunElaborate=1
RunImplementation=2 RunNoiseAnalysis=1 RunSynthesis=3 ShowView=5
ViewLayoutCmd=3 ViewTaskImplementedDesign=1 ViewTaskProjectManager=2
Other
GuiMode=3 BatchMode=0 TclMode=0 ISEMode=0
 
Core Statistics
Core Type=dds_compiler_v4_0
c_accumulator_width=26 c_amplitude=0 c_channels=1 c_has_ce=0
c_has_channel_index=0 c_has_phase_out=0 c_has_phasegen=1 c_has_rdy=0
c_has_rfd=0 c_has_sclr=0 c_has_sincos=1 c_latency=-1
c_mem_type=1 c_negative_cosine=0 c_negative_sine=0 c_noise_shaping=0
c_optimise_goal=0 c_output_width=12 c_outputs_required=2 c_phase_angle_width=12
c_phase_increment=1 c_phase_increment_value=0 c_phase_offset=0 c_phase_offset_value=0
c_por_mode=0 c_use_dsp48=0
Core Type=chipscope_icon_v1_04_a
c_build_revision=0 c_core_major_ver=1 c_core_minor_alpha_ver=97 c_core_minor_ver=2
c_core_type=1 c_major_version=12 c_mfg_id=1 c_minor_version=4
c_num_control_ports=1 c_part_idcode_register=0 c_use_bufr=0 c_use_control0=1
c_use_control1=0 c_use_control10=0 c_use_control11=0 c_use_control12=0
c_use_control13=0 c_use_control14=0 c_use_control2=0 c_use_control3=0
c_use_control4=0 c_use_control5=0 c_use_control6=0 c_use_control7=0
c_use_control8=0 c_use_control9=0 c_use_ext_bscan=0 c_use_jtag_bufg=1
c_use_new_parser=0 c_use_sim=0 c_use_softbscan=0 c_use_unused_bscan=0
c_use_xst_tck_workaround=1 c_user_scan_chain=1 c_xco_list=Number_Control_Ports=1;Use_Ext_Bscan=false;User_Scan_Chain=USER1;Enable_Jtag_Bufg=true;Use_Unused_Bscan=false;Use_Softbscan=false c_xdevicefamily=spartan6
Core Type=chipscope_ila_v1_03_a
c_build_revision=0 c_core_major_ver=1 c_core_minor_alpha_ver=97 c_core_minor_ver=2
c_core_type=2 c_data_depth=16384 c_data_width=1 c_ext_cap_pin_mode=0
c_ext_cap_rate_mode=0 c_ext_cap_use_reg=1 c_m0_tpid=0 c_m0_type=1
c_m10_tpid=10 c_m10_type=0 c_m11_tpid=11 c_m11_type=0
c_m12_tpid=12 c_m12_type=0 c_m13_tpid=13 c_m13_type=0
c_m14_tpid=14 c_m14_type=0 c_m15_tpid=15 c_m15_type=0
c_m1_tpid=1 c_m1_type=0 c_m2_tpid=2 c_m2_type=0
c_m3_tpid=3 c_m3_type=0 c_m4_tpid=4 c_m4_type=0
c_m5_tpid=5 c_m5_type=0 c_m6_tpid=6 c_m6_type=0
c_m7_tpid=7 c_m7_type=0 c_m8_tpid=8 c_m8_type=0
c_m9_tpid=9 c_m9_type=0 c_major_version=12 c_mcnt0_width=1
c_mcnt10_width=1 c_mcnt11_width=1 c_mcnt12_width=1 c_mcnt13_width=1
c_mcnt14_width=1 c_mcnt15_width=1 c_mcnt1_width=1 c_mcnt2_width=1
c_mcnt3_width=1 c_mcnt4_width=1 c_mcnt5_width=1 c_mcnt6_width=1
c_mcnt7_width=1 c_mcnt8_width=1 c_mcnt9_width=1 c_mfg_id=1
c_minor_version=4 c_num_ext_cap_pins=8 c_num_match_units=1 c_num_tseq_cnt=0
c_num_tseq_states=16 c_ram_type=1 c_srl16_type=2 c_tc_mcnt_width=1
c_timestamp_depth=512 c_timestamp_type=0 c_timestamp_width=32 c_trig0_width=24
c_trig10_width=1 c_trig11_width=1 c_trig12_width=1 c_trig13_width=1
c_trig14_width=1 c_trig15_width=1 c_trig1_width=1 c_trig2_width=1
c_trig3_width=1 c_trig4_width=1 c_trig5_width=1 c_trig6_width=1
c_trig7_width=1 c_trig8_width=1 c_trig9_width=1 c_tseq_cnt0_width=1
c_tseq_cnt1_width=1 c_tseq_type=1 c_use_atc_clkin=0 c_use_data=0
c_use_gap=0 c_use_inv_clk=0 c_use_mcnt0=0 c_use_mcnt1=0
c_use_mcnt10=0 c_use_mcnt11=0 c_use_mcnt12=0 c_use_mcnt13=0
c_use_mcnt14=0 c_use_mcnt15=0 c_use_mcnt2=0 c_use_mcnt3=0
c_use_mcnt4=0 c_use_mcnt5=0 c_use_mcnt6=0 c_use_mcnt7=0
c_use_mcnt8=0 c_use_mcnt9=0 c_use_rpm=1 c_use_storage_qual=1
c_use_tc_mcnt=0 c_use_trig0=1 c_use_trig1=0 c_use_trig10=0
c_use_trig11=0 c_use_trig12=0 c_use_trig13=0 c_use_trig14=0
c_use_trig15=0 c_use_trig2=0 c_use_trig3=0 c_use_trig4=0
c_use_trig5=0 c_use_trig6=0 c_use_trig7=0 c_use_trig8=0
c_use_trig9=0 c_use_trig_out=0 c_use_trigdata0=1 c_use_trigdata1=0
c_use_trigdata10=0 c_use_trigdata11=0 c_use_trigdata12=0 c_use_trigdata13=0
c_use_trigdata14=0 c_use_trigdata15=0 c_use_trigdata2=0 c_use_trigdata3=0
c_use_trigdata4=0 c_use_trigdata5=0 c_use_trigdata6=0 c_use_trigdata7=0
c_use_trigdata8=0 c_use_trigdata9=0 c_xco_list=Component_Name=ila_pro_0;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=16;Use_RPMs=true;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=16384;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=24;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=basic_with_edges;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=1;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=1;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=1;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=1;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=1;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=1;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=1;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=1;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=1;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=1;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=1;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=1;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=1;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=1;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=1;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic;Exclude_From_Data_Storage_16=false c_xdevicefamily=spartan6
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BSCAN_SPARTAN6=1 NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=165
NGDBUILD_NUM_FDC=1 NGDBUILD_NUM_FDCE=24 NGDBUILD_NUM_FDE=60 NGDBUILD_NUM_FDP=25
NGDBUILD_NUM_FDPE=50 NGDBUILD_NUM_FDR=73 NGDBUILD_NUM_FDRE=88 NGDBUILD_NUM_FDS=10
NGDBUILD_NUM_GND=10 NGDBUILD_NUM_INV=8 NGDBUILD_NUM_LDC=1 NGDBUILD_NUM_LUT1=79
NGDBUILD_NUM_LUT2=83 NGDBUILD_NUM_LUT3=33 NGDBUILD_NUM_LUT4=86 NGDBUILD_NUM_LUT5=3
NGDBUILD_NUM_LUT6=30 NGDBUILD_NUM_MUXCY=60 NGDBUILD_NUM_MUXCY_L=85 NGDBUILD_NUM_MUXF7=11
NGDBUILD_NUM_MUXF8=2 NGDBUILD_NUM_OBUF=24 NGDBUILD_NUM_RAMB16BWER=26 NGDBUILD_NUM_SRL16=24
NGDBUILD_NUM_SRL16E=1 NGDBUILD_NUM_SRLC16E=28 NGDBUILD_NUM_SRLC32E=35 NGDBUILD_NUM_VCC=12
NGDBUILD_NUM_XORCY=126
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BSCAN_SPARTAN6=1 NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FD=165 NGDBUILD_NUM_FDC=1
NGDBUILD_NUM_FDCE=24 NGDBUILD_NUM_FDE=60 NGDBUILD_NUM_FDP=25 NGDBUILD_NUM_FDPE=50
NGDBUILD_NUM_FDR=73 NGDBUILD_NUM_FDRE=88 NGDBUILD_NUM_FDS=10 NGDBUILD_NUM_GND=11
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=8 NGDBUILD_NUM_LDC=1 NGDBUILD_NUM_LUT1=79
NGDBUILD_NUM_LUT2=83 NGDBUILD_NUM_LUT3=33 NGDBUILD_NUM_LUT4=86 NGDBUILD_NUM_LUT5=3
NGDBUILD_NUM_LUT6=30 NGDBUILD_NUM_MUXCY=60 NGDBUILD_NUM_MUXCY_L=85 NGDBUILD_NUM_MUXF7=11
NGDBUILD_NUM_MUXF8=2 NGDBUILD_NUM_OBUF=24 NGDBUILD_NUM_RAMB16BWER=26 NGDBUILD_NUM_SRL16E=25
NGDBUILD_NUM_SRLC16E=28 NGDBUILD_NUM_SRLC32E=35 NGDBUILD_NUM_TIMESPEC=1 NGDBUILD_NUM_TS_TIMESPEC=1
NGDBUILD_NUM_VCC=13 NGDBUILD_NUM_XORCY=126